Electronics devices and capabilities have grown extremely common in daily life. Along with personal computers in the home, many individuals carry more than one productivity tool for various and sundry purposes. Most personal productivity electronic devices include some form of non-volatile memory. Cell phones utilize non-volatile memory in order to store and retain user programmed phone numbers and configurations when the power is turned off. PCMCIA cards utilize non-volatile memory to store and retain information even when the card is removed from its slot in the computer. Many other common electronic devices also benefit from the long-term storage capability of non-volatile memory in un-powered assemblies.
Non-volatile memory manufacturers that sell to the electronic equipment manufacturers require testers to exercise and verify the proper operation of the memories that they produce. Due to the volume of non-volatile memories that are manufactured and sold at consistently low prices, it is very important to minimize the time it takes to test a single part. Purchasers of non-volatile memories require memory manufacturers to provide high shipment yields because of the cost savings associated with the practice of incorporating the memory devices into more expensive assemblies with minimal or no testing. Accordingly, the memory testing process must be sufficiently efficient to identify a large percentage of non-conforming parts and preferably all non-conforming parts in a single test process.
As non-volatile memories become larger, denser and more complex, the testers must be able to handle the increased size and complexity without significantly increasing the time it takes to test them. Memory tester frequently run continuously, and test time is considered a major factor in the cost of the final part. As memories evolve and improve, the tester must be able to easily accommodate the changes made to the device. Another issue specific to testing non-volatile memories is that repeated writes to cells of the memories can degrade the overall lifetime performance of the part. Non-volatile memory manufacturers have responded to many of the testing issues by building special test modes into the memory devices. These test modes are not used at all by the purchaser of the memory, but may be accessed by the manufacturer to test all or significant portions of the memories in as little time as possible and as efficiently as possible. Some non-volatile memories are also capable of being repaired during the test process. The tester, therefore, should be able to identify: a need for repair; a location of the repair; the type of repair needed; and, must then be able to perform the appropriate repair. Such a repair process requires a tester that is able to detect and isolate a specific nonconforming portion of the memory. In order to take full advantage of the special test modes as well as the repair functions, it is beneficial for a tester to be able to execute a test program that supports conditional branching based upon an expected response from the device.
From a conceptual perspective, the process of testing memories is an algorithmic process. As an example, typical tests include sequentially incrementing or decrementing memory addresses while writing 0""s and 1""s into the memory cells. It is customary to refer to a collection of 1""s and 0""s being written or read during a memory cycle as a xe2x80x9cvectorxe2x80x9d, while the term xe2x80x9cpatternxe2x80x9d refers to a sequence of vectors. It is conventional for tests to include writing patterns into the memory space such as checkerboards, walking 1""s and butterfly patterns. A test developer can more easily and efficiently generate a program to create these patterns with the aid of algorithmic constructs. A test pattern that is algorithmically coherent is also easier to debug and facilitates the use of logical methods to isolate portions of the pattern that do not perform as expected. A test pattern that is generated algorithmically using instructions and commands that are repeated in programming loops consumes less space in tester memory. Accordingly, it is desirable to have algorithmic test pattern generation capability in a memory tester.
Precise signal edge placement and detection is also a consideration in the effectiveness of a non-volatile memory tester. In order to capture parts that are generally conforming at a median while not conforming within the specified margins, a non-volatile memory tester must be able to precisely place each signal edge relative in time to another signal edge. It is also important to be able to precisely measure at which point in time a signal edge is received. Accordingly, a non-volatile memory tester should have sufficient flexibility and control of the timing and placement of stimuli and responses from the Device Under Test (memory).
Memory testers are said to generate xe2x80x9ctransmitxe2x80x9d vectors that are applied (stimulus) to the DUT (Device Under Test), and xe2x80x9creceivexe2x80x9d vectors that are expected in return (response). The algorithmic logic that generates these vectors can generally do so without troubling itself about how a particular bit in a vector is to get to or from a particular signal pad in the DUT, as the memory tester contains mapping arrangements to route signals to and from pins.
Memory testers have interior test memory that is used to facilitate the test process. This interior test memory may be used for several purposes, among which are storing transmit vectors ahead of time, as opposed to generating them in real time, storing receive vectors, and storing a variety of error indications and other information concerning DUT behavior obtained during testing. (There are also housekeeping purposes internal to the operation of the memory tester that use SRAM and that may appear to fall within the purview of the phrase xe2x80x9cinterior memory.xe2x80x9d These are private to the internal operation of the tester, tend to not be visible at the algorithmic level, and are comparable to internal control registers. That memory is described as xe2x80x9cinterior control memory,xe2x80x9d and is excluded from what is meant herein by the term xe2x80x9cinterior test memory,xe2x80x9d which we use to describe memory used to store bit patterns directly related to the stimulus of, and response from, the DUT.) It is easy to appreciate that this interior test memory needs to operate at least as fast as the tests being performed; a very common paradigm is for the interior test memory (or some portion thereof) to be addressed by the same address (or some derivative thereof) as is applied to the DUT. What is then stored at that addressed location in interior test memory is something indicative of DUT behavior during a test operation performed on the DUT at that address. Algorithmic considerations within the test program may mean that the sequence of addresses associated with consecutive transmit vectors can be arbitrary. Thus, the interior memory needs to have the dual attributes of high speed and random addressability. SRAM comes to mind immediately as being fast, easy to control and tolerant of totally random addressing. Indeed, conventional memory testers have used SRAM as their interior test memory.
Unfortunately, SRAM is quite expensive, and this has limited the amount of interior test memory with which memory testers have had to work. The result is limits on memory tester functionality that are imposed by a shortage of memory. DRAM is significantly less expensive, but cannot tolerate random addressing and still perform at high speed.
DRAM can replace SRAM as the interior test memory in a memory tester. As briefly described in a simplified overview below, the problem of increasing the speed of DRAM operation for use as interior test memory can be solved by increasing the amount of DRAM used, in place of increasing its speed. Numbers of identical Banks of DRAM are treated as Groups. A combination of interleaving signals for different Banks of memory in a Group thereof and multiplexing between those Groups of Banks slows the memory traffic for any one Bank down to a rate that can be handled by the Bank. (For the reader""s convenience, we include a very abbreviated summary of this technique here, since much of its architectural aspects and associated terminology are useful in the explanation of the inventive subject matter that follows.)
A three-way multiplexing between three Groups of four Banks each, combined with a flexible four-fold interleaving scheme for signal traffic to a Group produces an increase in operating speed approaching a factor of twelve, while requiring only three memory busses. A round robin strategy for choosing the next Group for the multiplexer is simple and assures that the interleaving mechanism for each Group has the time it needs to complete its most recently assigned task. All interleaved accesses within a Group are performed upon a next Bank (within that Group), also selected by a simple round robin selection. In this configuration, each of the twelve Banks represents a duplicate instance of the entire available address space, and any individual write cycle might end up accessing any one of the twelve Banks. An implication is that, at the conclusion of testing, all twelve Banks must be investigated to learn what failures happened during testing of the DUT, since the history of any address or collection of addresses of interest will be spread out across all twelve Banks. A particular channel is thus represented by twelve bits (one bit from each Bank and whose bit position within the word for that Bank is determined by the channel).
It would be, however, awkward to have to (manually, as it were) individually consult all twelve Banks to discover failure information, so a utility mechanism has been provided to automatically xe2x80x9ccomposexe2x80x9d (merge) results of all twelve Banks during a read cycle at an address into a unified result that can be stored in one or all twelve Banks. This allows composed data to later be read at full speed.
At the top level of interior test memory organization there are four Memory Sets, each having its own separate and independent address space and performing requested memory transactions. Two are of DRAM as described above, and two are of SRAM. Each Memory Set has its own controller to which memory transactions are directed. As to externally visible operational capabilities, all four Memory Sets are essentially identical. They differ only in their size of memory space and how they are internally implemented: The SRAM Memory Sets do not employ multiplexing and interleaving, since they are fast enough to begin with.
The interior test memory of the tester is divided into four Memory Sets, two of which are xe2x80x9cinternalxe2x80x9d SRAM""s and two of which are xe2x80x9cexternalxe2x80x9d DRAM""s. To be sure, all this memory is physically inside the memory tester; the terms xe2x80x9cinternalxe2x80x9d and xe2x80x9cexternalxe2x80x9d have more to do with a level of integration. The SRAM""s are integral parts of a VLSI (Very Large Scale Integration) circuit associated with the tester""s central functional circuitry, while the DRAM""s are individual packaged parts mounted adjacent the VLSI stuff. The amount of SRAM is fairly small, (say, around a megabit per Memory Set) while the amount of DRAM is substantial and selectable (say, in the range of 128 to 1024 megabits per Memory Set). The SRAM Memory Sets are always present, and may be used for any suitable purpose, such as storing the expected content of a DUT that is a ROM (Read Only Memory). The DRAM Memory Sets are actually optional, and are typically used for creating a trace for subsequent analysis leading to repair, although there are also other uses. The tester does not enforce a distinction between the SRAM and DRAM Memory Sets, as to different purposes for which they may be used. Those distinctions arise mostly as a matter of size. The SRAM Memory Sets are small, while the DRAM Memory Sets are potentially huge. The person or persons creating the test programming make the decisions concerning how the various Memory Sets are to be used.
We have said that the memory tester to described herein performs tests in an algorithmic fashion. The manner in which this is accomplished is by having a programmable mechanism upon which can execute a program that provides stimulus and response activity for the DUT. The programmatic nature of such a mechanism means that, for example, a sequence of addresses or data values can be operationally produced, at the time they are to be used, by arithmetic methods encoded in the program, rather than by simply being an entry in a long list that is traversed one step at a time, from its beginning to its end. For comparison purposes, that latter mode of operation is how a so-called xe2x80x9cvector testerxe2x80x9d operates.
And while it is sometimes possible to write a test program in a general fashion that allows specific configuration to be delayed until a later time (e.g. the number of address bits is n, n to be supplied either at compilation or at run time, or the width of the data path is k-many bits, and k is supplied later), once a DUT is on hand to be tested, everything is at once specific. A DUT is tested on what we shall term a xe2x80x9cTest Sitexe2x80x9d that also has a specific collection of resources with which to perform testing. A memory tester may have a large number of Test Sites. A Test Site has its own programmable mechanism for executing code that performs algorithmic testing of a DUT. The usual way to describe the main attribute of a Test Site is by the number of electrical signals (pins, test points, or, to use the industry term, xe2x80x9cchannelsxe2x80x9d) that can be involved in the testing process. Here, the word xe2x80x9cinvolvedxe2x80x9d means one or both of xe2x80x9ccan be controlledxe2x80x9d and xe2x80x9ccan be measuredxe2x80x9d. An obvious issue that arises is how to deal with cases where the number of channels needed by a Test Site to test a particular DUT is not the same as the number of channels possessed by the Test Site.
If the number of channels possessed by a Test Site is normally sixty-four, and a particular DUT needs sixty, then that is a good match. If a DUT needs only thirty-two, then it would be desirable to somehow get two DUT""s onto a single Test Site. That can be done (it""s called Multi-DUT operation), but is not our present interest. Instead, we are presently concerned with the case where it takes one hundred twenty-eight or two hundred fifty-six channels to test a particular xe2x80x9cBIG DUTxe2x80x9d. The usual solution for this situation in a vector machine is to simply have an appropriate list of vectors per Test Site and then simultaneously perform their operations in parallel. But then we still have vector machine, and are denied the advantages of using an algorithmic machine. We should like a way to bore a Test Site out to be bigger than it was made, and yet still preserve algorithmic control of the result.
What to do?
A Test Station for a memory tester is comprised of one or more Test Sites that are each individually algorithmically controllable, that can each deal with as many as sixty-four channels, and that can be bonded together to form a Multi-Site Test Station of two or more Test Sites. Up to nine Test Sites can be bonded together as a single Multi-Site Test Station. Bonded Test Sites still operate at the highest speeds they were capable of when not bonded. To bring this about it is necessary to implement certain programming conventions and to provide certain housekeeping functions relating to simultaneous starting of separate test programs on the bonded Test Sites, and relating to propagation and synchronization of test program qualifier results among those separate test programs. There also needs to be a suspend/resume test program execution mechanism that assists in temporary program interruption to allow time for a change within one or more of the Test Sites of a measurement parameter, such as a voltage comparison threshold.